The present invention relates to a semiconductor device to be mounted using a lead frame. More particularly, the present invention relates to a semiconductor device in which semiconductor chips are disposed on both faces of a die pad or the lead frame, and also to a method of producing such a semiconductor device.
In a conventional a semiconductor-device mounting process, a single semiconductor chip is disposed on one face of a die pad of a lead frame made of a material such as a 42-alloy, Cu or the like, the bonding pads of the semiconductor chip and the inner leads of the lead frame are wire-bonded to each other through metallic fine wires made of Au, Al, Cu or the like, and the semiconductor chip, the bonding wires and the lead frame are sealed with an insulating resin to protect the semiconductor chip and the bonding wires from the external environment.
On the other hand, recent electronic machines, in particular, information machines, compact portable terminal machines and the like tend to have more functions and better performance. This increases the number of semiconductor devices to be mounted on an electronic machine. Accordingly, when there are used semiconductor devices each of which is formed by mounting a single semiconductor chip on one lead frame as conventionally done, it is difficult to satisfy the requirements for smaller, lighter and more economical electronic machines.
In this connection, a multi-chip package technology is proposed as one of means for providing smaller and lighter electronic machines without the functions and performance thereof injured. More specifically, a plurality of semiconductor chips are mounted on one semiconductor device, and such a semiconductor device is used to form an electronic machine. This lowers the number of semiconductor devices mounted on an electronic machine, and consequently reduces the total area where the semiconductor devices occupy in the electronic machine. That is, a plurality of semiconductor chips are made in the form of a single package to reduce the number and mounting area of semiconductor devices mounted on an electronic machine. Thus, the electronic machine can be made in a smaller and lighter design, yet assuring the functions and performances required for the electronic machine.
The following description will discuss an example of a currently proposed multi-chip package technology.
A semiconductor device shown in FIG. 14a is formed by technique disclosed in Japanese Patent Laid-Open Publication H5-47999. In this semiconductor device, two lead frames 30a, 30b have die pads 31a, 31b on one faces of which semiconductor chips 32a, 32b are mounted, and the lead frames 30a, 30b are laminated to each other through an insulating film 33 and sealed with resins 29, thus forming a multi-chip package. FIG. 15 shows the process of producing this semiconductor device. As shown in FIG. 15, one semiconductor chip (not shown) is mounted on one face of the die pad 31a of one lead frame 30a, and then the semiconductor chip and that face of the lead frame 30a on which the semiconductor chip has been mounted, are sealed with the resin by transfer molding. Likewise, a semiconductor chip (not shown) is mounted on one face of the die pad 31b of the other lead frame 30b, and then the semiconductor chip and that face of the lead frame 30b on which the semiconductor chip has been mounted, are sealed with the resin by transfer molding. These two lead frames 30a, 30b of which only one faces have been sealed with resins, are laminated to each other through the insulating film 33. In the following description, such a semiconductor device is called a semiconductor device having a multi-layer lead frame.
A semiconductor device shown in FIG. 14b, is formed by technique disclosed in Japanese Patent Laid-Open Publications H1-272144 or H5-121462. In this semiconductor device, two semiconductor chips 32a, 32b are disposed on both faces of a die pad 31 of one lead frame 30 through adhesive layers 34a, 34b made of conductive adhesives or the like, thus forming a multi-chip package. FIG. 16 shows the process of producing this semiconductor device. As shown in FIG. 16a, one semiconductor chip 32a is mounted on one face of the die pad 31 of the lead frame 30 and then subjected to wire-bonding. As shown in FIG. 16b, the semiconductor chip 32a is sealed with resin 35a in one transfer molding die 39. As shown in FIGS. 16c, 16d, the semiconductor chip 32b is disposed on the other face of the lead frame 30, and then sealed with resin 40 in another transfer molding die 39. In the following description, such a semiconductor device is called a semiconductor device having a single-layer lead frame.
The following description will discuss the advantages and disadvantages of the conventional semiconductor device using a multi-layer lead frame as shown in FIG. 14a and the conventional semiconductor device using a single-layer lead frame as shown in FIG. 14b.
The semiconductor device having a multi-layer lead frame in FIG. 14a has the arrangement that two lead frames on which semiconductor chips are mounted, are laminated to each other. Accordingly, one semiconductor device requires two lead frames. This additionally requires the material cost, processing cost and the like of the lead frame and the insulating film. Further, there are required a process of and facilities for laminating the lead frames, thus also increasing the production cost. When only one faces of the lead frames are sealed with resins as shown in FIG. 15, the other faces of the lead frames opposite to the resin-sealed faces, are exposed. To increase the yield of lamination of two lead frames to be conducted at a later step, it is required to design and machine transfer molding dies with high precision such that no sealing resins seep out to prevent resin burrs from sticking to the exposed lead frame faces. This increases the transfer molding dies in cost.
In a semiconductor device having a single-layer lead frame, the number of the member and the number of production steps are reduced and the molding dies may not be so precise as compared with the semiconductor device having a multi-layer lead frame. Thus, the production cost is cheaper. As shown in FIG. 16, however, at least two sets of transfer molding dies and at least two sets of sealing devices are required in the transfer molding steps for distinguishing the obverse of the package from the reverse thereof. This increases the installation cost. Further, when changing the kind of semiconductor device in the production line, transfer molding dies should be replaced twice. It is therefore difficult to flexibly comply with the production of many kinds each in a small quantity.
As thus discussed, there are advantages and disadvantages in the semiconductor device having a single-layer lead frame and the semiconductor device having a multi-layer lead frame. The following description will discuss the common problems in the both types.
In Japanese Patent Laid-Open Publication H1-272144 above-mentioned, FIG. 7 and FIG. 7x show the arrangement of a semiconductor device having a multi-layer lead frame in which the inner leads of the lead frames are wire-bonded to the bonding pads of the semiconductor chips. In such an arrangement, however, if the semiconductor chips are different in operational frequency and voltage, there occurs crosstalk of electric signals among the inner leads. This involves the likelihood that the semiconductor device is considerably lowered in characteristics. Further, it is not easy to take out two signals, as separated from each other, from outer leads of two laminated lead frames.
In such a case, it is required to employ a connection method as shown in FIG. 5 of Japanese Patent Laid-Open Publication H1-272144. FIGS. 17a and 17b attached to the present application illustrate a connection method equivalent to that in FIG. 5 of the laid-open publication above-mentioned, which connection method is applied to a semiconductor device having two semiconductor chips each mounted on each of both faces of a die pad. FIG. 17a is a perspective view illustrating how to wire-bond the bonding pads of semiconductor chips 32a, 32b and inner leads 37 of a lead frame 30 in a semiconductor device having a single layer lead frame. FIG. 17b is a plan view illustrating the arrangement of the electrodes of outer leads of the semiconductor device which is sealed with resin. In FIG. 17a, inner leads 37a1 to 37a8 are connected to the bonding pads of the first semiconductor chip 32a disposed at the obverse face in FIG. 17a through bonding wires, and inner leads 37b1 to 37b8 are connected to the bonding pads of the second semiconductor chip 32b disposed at the reverse face in FIG. 17a through bonding wires 36. As shown in FIG. 17a, the adjacent inner leads are alternately connected to the bonding pads of the first semiconductor chip 32a and the bonding pads of the second semiconductor chip 32b. Accordingly, as shown in FIG. 17b, a semiconductor device 29 sealed with resin is arranged such that outer lead terminals 38a1 to 38a8 connected to the first semiconductor chip 32a and outer lead terminals 38b1 to 38b8 connected to the second semiconductor chip 32b are alternately disposed.
In a semiconductor device having a single-layer lead frame, as disclosed in FIG. 5 of Japanese Patent Laid-Open Publication H1-272144, the adjacent inner leads are alternately connected to the bonding pads of the obverse and reverse semiconductor chips. Such an arrangement is inevitably adopted for the following reasons. In a semiconductor device having a large number of inner leads and a large number of bonding pads of semiconductor chips, it is required to dispose the inner leads and the bonding pads such that they are in close proximity to one another substantially in the entire area of each of the sides of the semiconductor chips. For example, if, in FIG. 5 of the publication above-mentioned, three adjacent inner leads are connected to bonding pads of the same semiconductor chip, the lengths of the bonding wires become excessively long. Accordingly, the bonding wires greatly flow due to the pressure given by resin flow at a transfer molding step or the like (a so-called "wire flow" takes place). This involves the likelihood that the bonding wires come in contact with one another, that the bonding wires and the semiconductor chips come in contact with each other and that bonding wires are disconnected.
However, when the adjacent inner leads are alternately connected to two semiconductor chips as conventionally done, the distance between adjacent inner leads is as narrow as 120 to 250 .mu.m. When the semiconductor chips 32a, 32b are different in operational frequency and voltage, crosstalk of electric signals occurs among adjacent inner leads because the adjacent inner leads are connected to different semiconductor chips, respectively. This involves the likelihood that the semiconductor device is remarkably lowered in characteristics. Further, the conventional arrangement above-mentioned is still disadvantageous in that the bonding wires become uneven in length and that some bonding wires are inevitably excessively long. In particular, when the number of lead frames is increased, the distance between bonding wires at each frame corner is small. Accordingly, when a so-called wire flow occurs at the transfer molding step, there is a high probability that the bonding wires come in contact with one another.
Thus, not only a semiconductor device having a multi-layer lead frame, but also a semiconductor device having a single-layer lead frame are possibly lowered in characteristics. Further, local reduction in distance between bonding wires or a presence of some excessively long bonding wires possibly lowers the production yield and reliability of semiconductor devices.
The following description will discuss another problem. A semiconductor device having a single-layer lead frame is produced in a manner as shown in FIGS. 18a and 18b. That is, after a wire-bonding step is conducted on a first semiconductor chip 32a mounted on one face of a die pad 31, a lead frame 30 is turned over and a wire-bonding step is conducted on a second semiconductor chip 32b mounted on the other face of the die pad 31. At this time, there is a possibility that the bonding wires 36 already disposed at the reverse face, come in contact and interfere with a part of a heating/supporting stand 42 for supporting and heating the lead frame 30. When such an interference occurs, the already disposed bonding wires 36 may be cut or deformed to lower the semiconductor device in reliability. The lead frame is machined such that each distance between adjacent inner leads is generally as fine as hundreds .mu.m. Accordingly, it is extremely difficult to hold a specific inner lead and to make a highly precise heating/supporting stand 42 for providing a space such that already bonded wires do not come in contact and interfere with the heating/supporting stand 42. Consequently, the installation cost is remarkably increased in order to satisfy the requirements above-mentioned.
The following description will discuss a further problem regarding the shape of each inner lead. Generally, there are present, as the electrodes of a semiconductor chip, electrodes for receiving and supplying a signal and power electrodes for supplying an electric power to semiconductor chips. In a semiconductor chip in which power consumption is relatively large, there are instances where a plurality of high- or low-potential electrodes of the power electrodes are connected to a common inner lead in order to prevent bonding wires from being disconnected due to fusing to achieve a high-speed operation of the semiconductor chip. In a conventional lead frame, however, the connection is made as shown in FIG. 19. That is, the number of bonding wires which can be connected to one inner lead is limited. Further, when intended to connect a plurality of bonding pads disposed at positions remote from one another, to one inner lead through bonding wires, these bonding wires inevitably cross other bonding wires. Thus, these intersecting bonding wires may possibly come in contact with one another.